Publications of Creative Hardware Laboratory


Chronologically :  2010  2009   2008   2007   2006  2005  2004  2003  2002  2001-1987

2010

  1. Jewajinda, Y. and Chongstitvatana, P., "FPGA-based Online-learning using Parallel Genetic Algorithm and Neural Network for ECG Signal Classification,"  Proc. of ECTI Conf., 19-21 May 2010, Chiengmai, Thailand. (Best paper award).  ( pdf )

2009

  1. Wattanavekin, T., Suntharasantic, S., Kriengwattanakul, A., Wongphati, M. and Chongstitvatana, P., "The design of embedded systems for RoboCup Soccer Team : Plasma-Z," Int. Conf. on Embedded Systems and Intelligent Technology, Pattaya, Thailand, Feb 11-13, 2009. ( pdf )
  2. Chuengsatiansup, K., Sajjapongse, K., Kruapraditsiri, P., Chanma, C., Termthanasombat, N., Suttasupa, Y., Sattaratnamai, K., Pongkaew, E., Udsatid, P., Hattha, B., Wibulpolprasert, P., Usaphapanus, P., Tulyanon, N., Wongsaisuwan, M., Wannasuphoprasit, W., Chongstitvatana, P., "Plasma-RX: Autonomous Rescue Robots," IEEE Int. Conf. on Robotics and Biomimetics, Feb 21-26, 2009, Bangkok, Thailand. (preprint)
  3. Jewajinda, Y., Chongstitvatana, P., "Hardware architecture and FPGA implementation of a parallel elitism-based compact genetic algorihm," IEEE Region 10 Annual International Conference, Singapore, Nov 23-26, 2009.

2008

  1. Jewajinda, Y. and Chongstitvatana, P.,"FPGA Implementation of a Cellular Compact Genetic Algorithm",  NASA/ESA Conference on Adaptive Hardware and Systems, 22-25 June 2008, Netherlands, pp.385-390.  ( pdf )
  2. Thontirawong, P. and Chongstitvatana, P., "A Low-Resource AES Encryption Circuit Using Dynamic Reconfiguration", Int. Joint Conf. on Computer Science and Software Engineering, Thailand, 7-9 May 2008.  ( pdf )
  3. Jewajinda, Y. and Chongstitvatana, P.,"FPGA Implementation of a Cellular Univariate Estimation of Distribution Algorithm and Block-based Neural Network as an Evolvable Hardware", IEEE Congress on Evolutionary Computation, Hong Kong, June 1-6, 2008, pp.3365-3372. ( pdf )
  4. Thontirawong, P. and Chongstitvatana, P., "Augmenting a Stack-based Virtual Machine with One-address Instructions for Performance Enhancement", Int. Conf. on Embedded Systems and Intelligent Technology, Bangkok, Feb 27-29, 2008. ( pdf )

2007

  1. Sripornprasert, J. and Chongstitvatana, P., "The AES encryption circuit on a reconfigurable hardware", Electrical Engineering, Electronics, Computer, Telecommunications and Information Technology (ECTI) International Conference, Chiang Rai, Thailand, 9-12 May 2007, pp.1139-1142.  ( pdf  )
  2. Satayavibul, C. and Chongstitvatana, P., "An embedded processor with instruction packing", Electrical Engineering, Electronics, Computer, Telecommunications and Information Technology (ECTI) International Conference, Chiang Rai, Thailand, 9-12 May 2007, pp.1135-1138.  ( pdf  )
  3. Lertteerawattana, W., Jedsadawaranon, T. and Chongstitvatana, P., "Instruction Packing for a 32-bit Stack-Based Processor", International Joint Conference on Computer Science and Software Engineering, Thailand, 2-4 May 2007, pp.126-130.  ( pdf  )  ( presentation  )

2006

  1. Chongstitvatana, P., "Stack Frame Caching", invited paper in Proc. of National Conf. on Computer Science and Engineering, Khon Kan, Thailand, 23-25 Oct. 2006.  ( pdf  )
  2. Jewajinda, Y. and Chongstitvatana, P., "A Cooperative Approach to Compact Genetic Algorithm for Evolvable Hardware",  IEEE World Congress on Computational Intelligence, Vancouver, Canada, July 16-21, 2006, pp.2779-2786.  ( pdf  )
  3. Sattayawiboon, C., Sripornprasert, J., Tansutthiwess,  S., Tonteerawong, P., and Chongstitvatana, P., "A stack processor with integrated display circuit for a low cost CD-ROM reading device", ECTI International Conference, May 10-13, Thailand, 2006.

2005

  1. Chongstitvatana, P., "A compact code 16-bit processor for embedded applications", Joint conf. of computer science and software engineering, Nov 2005, Thailand. ( pdf )
  2. Chongstitvatana, P., "Self-generating systems: how to a 10,000,000_2 line compiler assembles itself", invited paper, 8th National Computer Science and Engineering Conference, Bangkok, Thailand, October 27-28, 2005. ( pdf )
  3. Burutarchanai, A., Nanthanavoot, P. and Chongstitvatana, P., "Design of an embedded TCP/IP internet appliance", 8th National Computer Science and Engineering Conference, Bangkok, Thailand, October 27-28, 2005.
  4. Nanthanavoot, P., Burutarchanai, A., and Chongstitvatana, P., "Instruction packing for a 32-bit resource efficient processor," National Science and Technology Development Agency (NSTDA) Annual Conference, Thailand, 27-30 March 2005 (in Thai).   (English abstract)  ( preprint )

2004

  1. Burutarchanai, A., Nanthanavoot, P., Aporntewan, C., and  Chongstitvatana, P., "A stack-based processor for resource efficient embedded systems", Proc. of IEEE TENCON 2004, 21-24 November 2004, Thailand. ( pdf )
  2. Burutarchanai, A., Kotrajaras, V. and Chongstitvatana, P.,  "A fast instruction fetch unit for an embedded stack processor", Proc. of  Int. Conf. on Information and Communication Technologies (ICT 2004), 18-19 November, 2004. Thailand. ( pdf )
  3. Burutarchanai, A., and Chongstitvatana, P., "Design of a two-phased clocked control unit for performance enhancement of a stack processor", National Computer Science and Engineering Conference, Thailand, 21-22 Sept. 2004, pp.114-119. (English abstract) (pdf  in Thai)
  4. Nanthanavoot P. and Chongstitvatana, P., "Code-Size Reduction for Embedded Systems using Bytecode Translation Unit", Conf. of Electrical/Electronics, Computer, Telecommunications, and Information Technology (ECTI), Thailand, 13-14 May 2004. ( pdf )

2003

  1. Chongstitvatana, P., "The art of instruction set design", invited paper in Conf. of Electrical Engineering, Thailand, 2003. ( pdf )
  2. Kotrajaras, N., Chongstitvatana, P., "Nibbling Java byte code of resource-critical devices", National Computer Science and Engineering Conference, Thailand, 2003.  ( pdf )
  3. Piromsopa, K., Bavonparadon, P. and Chongstitvatana, P., "Hardware multiplexing: towards a resource efficient reconfigurable processor", 3rd International Symposium on Communications and Information Technologies,  3-5 September 2003, Thailand.  ( pdf )
  4. Chalermsap Sankavijit, Somboon Sangvongvanit, Prabhas Chongstitvatana, Error Analysis for Fixed-point Interval Arithmetic in Embedded System Programming, Conf. of Electrical Engineering, Thailand, 2003. (in Thai) ( pdf )

2002

  1. Chongstitvatana, P. and Kotrajaras, V., "Instruction compression by nibble coding: war on the old front", IEEE Thailand section: Silver Jubilee Symposium, 15 Nov 2002.  ( pdf )
  2. Nanthanavoot, P. and Chongstitvatana, P., "Development of a data reading device for a CD-ROM drive with FPGA technology", Conf. of Electrical Engineering, Thailand, 2002.  ( pdf )
  3. Bavonparadon, P. and Chongstitvatana, P., "RTL formal verification of embedded processors", IEEE  Int. Conf on Industrial Technology, Vol.1, 2002, pp. 667-672  ( pdf )

2001-1987

  1. Piromsopa, K, Aportewan, C. and Chongstitvatana, P., "An FPGA implementation of a fixed-point square root operation", Inter. Symposium on Communications and Information Technology, Nov. 14-16, Thailand, 2001, pp. 587-589.  (  pdf  )
  2. Piromsopa, K., Sowanwanichakul, B. and Chongstitvatana, P., "Reconfigurable embedded web server: towards a flexible Internet appliance", Proc. of 1st Seminar on Collaboration in Computer Communications and IC Design Technologies in Thailand, Songkla, Thailand, December, 2000, pp.63-70. ( pdf )
  3. Aporntewan, C., and Chongstitvatana, P., "An on-line evolvable hardware for learning finite-state machine", Proc. of Int. Conf. on Intelligent Technologies, Bangkok, December 13-15, 2000, pp.125-134. ( pdf )
  4. Wongsiriprasert, C. and Chongstitvatana, P., "Performance comparison between two virtual machine interpreters : stack-based vs. register-based", Proc. of 3rd Annual National Symposium on Computational Science and Engineering, Bangkok, 1999, pp. 401-406.  (pdf)
  5. Manovit, C., Aportewan, C. and Chongstitvatana, P., "Comparison of Technology-based and State-based Representations for the Synthesis of Synchronous Sequential Logic from Partial Input/output Sequences", 21th Electrical Engineering Conference, Thailand, 1998, pp.210-213. (pdf)
  6. Kongmunvattana, A. and  Chongstitvatana, P.," A FPGA-based Behavioral Control System for a Mobile Robot", 1998 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '98), pp.759-762. (pdf)
  7. Manovit, C.,  Aporntewan, C., and Chongstitvatana, P., "Synthesis of Synchronous Sequential Logic Circuits from Partial Input/Output Sequences", Proc. of 2nd Int. Conf. on Evolvable Systems  (ICES98), Lausanne, Switzerland, 1998, pp. 98-105.  (pdf)
  8. Aportenwan, C., Manovit, C. and Chongstitvatana, P., "Synthesis of synchronous sequential logic circuit by genetic algorithm", Proc. of The Second Annual National Symposium on Computational Science and Engineering, pp. 234-243, Bangkok, March 25-27, 1998.
  9. Taechashong, P. and Chongstitvatana, P., "A VLSI design of a load/store unit for a RISC microprocessor", Proc. of The Second Annual National Symposium on Computational Science and Engineering, pp. 244-248, Bangkok, March 25-27, 1998. (pdf)
  10. Chongstitvatana, P., "Post processing optimization of byte-code instructions by extension of its virtual machine", 20th Electrical Engineering Conference, Thailand, 1997. (pdf)
  11. Kongmunvattana, A. and Chongstitvatana, P., "An FPGA design of DES algorithm", 17th Electrical Engineering Conference, Thailand, 1994. (pdf)
  12. Wongsamethin, O.,  Kienprasit, R. and  Chongstitvatana, P., "Fast Fourier Transform by a Digital Signal Processor", 10th Electrical Engineering Conference, Thailand, 1987. (in Thai)

last update 28 Nov 2010