How to design a processor
Advice: Keep it simple
The most reliable part is the part that is not in the design !
Instruction set
Microarchitecture
Control unit
Microprogramming
Tools
Reading
This page aims to promote "how to" in processor design. Promoting
the National IC Design
Contest (hosted by National Electronics and Computer Technology of
Thailand) for the digital design part.
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Design an instruction set
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Design a microarchitecture
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Draw functional blocks
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Write microsteps
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Write a simulator
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Write an assembler
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Implement the microarchitecture
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Implement the control unit
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Test and Debug (the most time consuming task)
Try to design a "minimum" instruction set, the set that covers the intended
applications. The number of instruction effects the complexity of
the design and the testing, especially the testing.
Instruction Set
Examples
8-bit Z80
Z8 6809
2650 AVR
16-bit S1
PDP-11 CompactRISC
( ref )
32016
32-bit 32032
S2 ARM
My collection CPU3
FRIDAY
Microarchitecture
S1
FRIDAY
hardwired
microprogrammed
Microprogramming
S1 microprogramming
Tools
Assembler
a3 (for CPU3) as2
(for S2)
Simulator CPU3
S1
(see tools section) S2
Microprogramming S1
microprogram (see tools section)
S2 processor tools
Reading
My papers on intruction set design
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extended virtual machine: Chongstitvatana, P., "Post processing
optimization of byte-code instructions by extension of its virtual machine",
20th Electrical Engineering Conference, Thailand, 1997. (pdf)
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comparing register and stack: Wongsiriprasert, C. and Chongstitvatana,
P., "Performance comparison between two virtual machine interpreters :
stack-based vs. register-based", Proc. of 3rd Annual National Symposium
on Computational Science and Engineering, Bangkok, 1999, pp. 401-406.
(pdf)
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instruction compression: Chongstitvatana, P. and Kotrajaras,
V., "Instruction compression by nibble coding: war on the old front", IEEE
Thailand section: Silver Jubilee Symposium, 15 Nov 2002. ( pdf
)
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instruction set design: Chongstitvatana, P. "The Art of Instruction
Set Design", Invited paper in Proc. of Electrical Engineering Conference,
Thailand, 2003. ( pdf )
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futuristic architecture: hardware multiplexing: Piromsopa,
K., Bavonparadon, P. and Chongstitvatana, P., "Hardware multiplexing: towards
a resource efficient reconfigurable processor", 3rd International Symposium
on Communications and Information Technologies, 3-5 September 2003,
Thailand. (
pdf )
last update 9 Oct 2003
P. Chongstitvatana