TX1 

instruction format

L op:4 ads:12
R op:4 xop:4 r1:4 r2:4
I op:4 xop:4 d:8

instruction set

0 nop                                  L
1 lda ads    ac = M[ads]  L
2 sta ads    M[ads] = ac  L
3 jmp ads    PC = ads  L
4 jt ads     if F!=0 PC = ads L
5 jf ads     if F==0 PC = ads L
6 call ads    savretads, PC = ads L

13 0 clr r2      R[r2] = 0             R
13 1 inc r2      R[r2] += 1            R
13 2 dec r2      R[r2] -= 1            R

14 0 add r2 ac = ac + R[r2] R
14 1 sub r2 ac = ac - R[r2] R
14 2 and r2  ac = ac & R[r2]   R
14 3 or r2  ac = ac | R[r2]   R
14 4 xor r2  ac = ac ^ R[r2]   R
14 5 eq r2 F = ac == R[r2]    R
14 6 lt r2 F = ac < R[r2]   R
14 7 le r2 F = ac <= R[r2]   R
14 8 gt r2 F = ac > R[r2]   R
14 9 ge r2 F = ac >= R[r2]   R

14 10 mva r2ac = R[r2]     R
14 11 mvr r2R[r2] = ac     R
14 12 ldx r2ac = M[BP+R[r2]] R
14 13 stx r2M[BP+R[r2]] = ac R

15 0 addi #d ac = ac + d    I
15 1 subi #d ac = ac - d   I
15 2 andi #d ac = ac & d   I
15 3 ori #d ac = ac | d   I
15 4 xori #d ac = ac ^ d   I
15 5 eqi #d F = ac == d    I
15 6 lti #d F = ac < d     I
15 7 lei #d F = ac <= d   I
15 8 gti #d F = ac > d   I
15 9 gei #d F = ac >= d   I

15 10 mvi #dac = d  I
15 11 trap #d    special               I
15 12 retPC = retads  -
15 13 not        ac = ~ac              -

mostly r1 = 0 in R format

23 june 2017
