
number of cycle 

register: read-mod-write  2 cycles
mem read: 2 cycle
jump: 1 cycle


<fetch>
IR = M[PC], PC+1
decode

<ld> 
mread(IR:ads)
LDS[ls] = din

<st>
...

<ldx>
ads = R[r1]+R[r2]
mread(ads)
LDS = din
<stx>
...

<ldr>
R = LDS
<str>
...

<ldw>
mread(IR:ads)
LDS = din

<bc>
R = LDS[ls]

<add>
t = op(R[r1],R[r2])
R[r3] = t

<jmp>
PC = ads

<mvt>
if T then R[r1] = R[r2]


summary

fetch  2
execute
ld,st  2
ldx,stx 3
ldr,str 1
ldw 2
bc 1
add,... 2
jmp  1
mvt 1


29 Dec 2012



