Cache design  Computer Architecture lecture 1997

Cache is a high speed memory intends to speed up the processor-memory
access.  (VM is intended to speed up processor-disk access).
Cache is a 'shadow' of main memory and its size is smaller than
main memory (due to high cost of cache memory, as it is of higher
speed).  Mapping from memory-cache is the topic of cache design.
Cache can be organised into various type according to mapping methods:
 Fully associative
 Direct Map
 Set associative

Because cache size is smaller than real address space, part of 
address is used to indicate which location of cache 


 Design parameters : cache size, line size, m-way,
 replacement policy : LRU, random

cache size : 128 256 512 1024 2048 bytes
 (actually the trace has instruction at byte boundary
but data at word boundary and data is access as word)
 line size : 1 2 4 8
 m-way : 1 2 4

the decoding scheme for the field : tag, index, and offset
is important.  ( where / is integer divide )
 a = ads / L   where L is linesize
 offset = ads mod L
 numofslot = cachesize / ( m-way * linesize )
 index = a mod numofslot
 tag = a / numofslot
 
present results in graphic form
plot: hit ratio (y), cachesize (x), for all line sizes for each
m-way.
plot: hit ratio (y), m-way (x), for all line sizes for each cache size.

  



















