Cache Simulator

Supplementary material for Computer Architecture: Design and Analysis (2026 edition) · Krerk Piromsopa, Ph.D. · Chulalongkorn University

CacheSim is a configurable direct-mapped cache simulator written in C. It reads a load-address trace (one hex address per line) and reports hit count, miss count, and miss rate. Students modify the header file parameters and the source code to explore how cache size, block size, and associativity affect miss rate — the key exercise in the Cache activity of Appendix D.

Downloads

📄 CacheSim.c Simulator source (C) Download

📋 CacheSim.h Configuration header Download

📊 gcc_ld_trace.txt GCC load-address trace (50 k entries) Download

📊 go_ld_trace.txt Go load-address trace (50 k entries) Download

Quick Start

Compile and run on Linux / macOS (any C99 compiler):

$ gcc -O2 -o cachesim CacheSim.c
$ ./cachesim gcc_ld_trace.txt
CacheSim v.2026
HIT:  47832  MISS:   2168  Total:  50000  Miss rate: 4.34%

On Windows (MinGW / WSL):

$ gcc -O2 -o cachesim.exe CacheSim.c
$ cachesim.exe gcc_ld_trace.txt

Configuration Parameters (`CacheSim.h`)

Change these #define values to model different cache configurations. The bit-field lengths must satisfy: TAGLEN + INDEXLEN + OFFSETLEN = 32.

Parameter	Default	Meaning
`CACHE_SIZE`	1024	Total cache size in bytes
`INDEX_SIZE`	256	Number of cache lines (= CACHE_SIZE / BLOCK_SIZE)
`BLOCK_SIZE`	4	Block (cache line) size in bytes
`TAGLEN`	22	Bits used for the tag field
`INDEXLEN`	8	Bits used to index into the cache (log₂ INDEX_SIZE)
`OFFSETLEN`	2	Bits used for the block offset (log₂ BLOCK_SIZE)

Example: To model a 4 KB direct-mapped cache with 16-byte blocks:
BLOCK_SIZE = 16, INDEX_SIZE = 256, OFFSETLEN = 4, INDEXLEN = 8, TAGLEN = 20

Address Trace Format

Each line of the trace file contains a single load address in lowercase hex with the 0x prefix:

0x0804c318
0x0804a050
0x0804a018
0x0804a0cc
...

You can generate your own traces using valgrind's lackey tool or by instrumenting programs with Valgrind / PIN.

$ valgrind --tool=lackey --trace-mem=yes ./my_program 2>&1 \
    | grep "^I\|^ L" | awk '{print $2}' | sed 's/,.*//' > my_trace.txt

Exercise Tasks (Appendix D)

The Appendix D cache activity asks you to run CacheSim with the two provided traces and fill in the following experiments:

Block size tradeoff on a direct-mapped cache — vary BLOCK_SIZE (4, 8, 16, 32 bytes) and CACHE_SIZE (4 KB, 8 KB, 16 KB, 32 KB). Record the miss rate for each combination.
Associativity — extend CacheSim.c to support N-way set-associative caches with LRU and Round-Robin replacement. Compare miss rates for 2-way and 4-way at multiple cache sizes.
Analysis — plot miss rate vs. cache size for each block size, and discuss the tradeoffs observed.

Tip: The simulator currently implements a simple direct-mapped cache. To implement N-way associativity you will need to change the Cache struct into an array of N ways, add an LRU counter, and update the access() function accordingly. This is intentionally left as a programming exercise.

File Structure

CacheSim/
├── CacheSim.c          ← simulator source
├── CacheSim.h          ← configuration + struct definition
├── gcc_ld_trace.txt    ← GCC benchmark load-address trace
└── go_ld_trace.txt     ← Go benchmark load-address trace