Instruction packing for a 32-bit resource efficient processor
Ref
Nanthanavoot, P., Burutarchanai, A., and Chongstitvatana, P.,
"Instruction packing for a 32-bit resource efficient processor,"
National Science and Technology Development Agency (NSTDA) Annual
Conference, Thailand, 27-30 March 2005.
Abstract
This paper proposed a design of 32-bit stack processor for embedded
systems. The design has an advantage of resource efficiency. The
architecture is stack-based therefore it is simple and consumes less
resource. The instruction set format is based on bytecode. This work
proposed a technique of instruction packing which packs several
instructions into a 32-bit instruction unit. The result from the
experiment shows that the execution speed of packed-instructions has
speed up 2.12 times over executing normal bytecode, while the size of
benchmark programs is kept small though the total size of packed
instruction is bigger than the normal bytecode.
Keywords: Processor, Instruction packing, Bytecode instruction