2110793  Advanced Topics in Digital Systems   2013

  http://www.cp.eng.chula.ac.th/~piak/teaching/ads/ads2013/ads2013-index.htm
alternate host  https://db.tt/JmbVLR38

Class meet on Wed 9:30-11:00  Eng 3403, Thurs 9:30-11:00 Eng 3320

Syllabus

This course concentrates on the components and architecture of  modern supercomputers.  Operating systems and compilers will be discussed.  Hand-on of the implementation of processors and operating systems under simulation will be covered.  Advanced topics on the future exaflop machines and Graphic Processing Units will be discussed.

Assesment

homework          20%
midterm project   30%
final                     50%

Announcements

21 Feb 2014   Final will be  take-home questions, issues on 28 Feb 2014.  Hand-in before Friday 7 March 2014, 4pm.

Topics

Exaflop machine
Processor
Instruction Set Architecture
Memory subsystems
Operating Systems
Graphic Processing Units
(research in computer architecture)
Network on Chip
Internet of Things
Content addressable memory

Lecture

Exascale computing (ppt )
Operating systems and task scheduling  basic OS concepts,   Nos  (Nut Operating System)  Nos services 
    semaphore:  flash demo from William Stallings, U. of Queensland
    lecture from Matt Welsh, Harvard,   semaphores.pdf 
Nut operating system implementation
    nos1.txt  (process)  nos2.txt  (with semaphore)  nos4.txt (with mailbox)
Graphic Processing Unit
Cache memory  
Content Addressable Memory  ieee-article    intro-website
Content Addressable Memories by Vahid Tabatabaee Fall 2007, U. of Maryland  ( ppt )
Network on Chip
    General introduction (IEEE computer, 2002) 
          http://infoscience.epfl.ch/record/165542/files/00976921.pdf
    Recent development (International Symposium on Computer Architecture, 2011)
          http://pages.cs.wisc.edu/~hestness/links/KNOC_ISCA11.pdf
    Commercial development
          http://www.design-reuse.com/articles/10496/a-comparison-of-network-on-chip-and-busses.html

Future Internet: Internet of Things :  
   Chen, Yen-Kuang, "Challenges and Opportunities of Internet of Things," Design Automation Conference, 2012, pp.383 - 388 ( pdf )

Homework

1)   Read the article "the top in flops" (link below) and prepare to discuss it in class.
2)   Read and prepare to discuss The Opportunities and Challenges of Exascale Computing
3)  Write in pseudo code,  create a singly linked list of ten items.
4)   Write one task program, include it in Nos and compile and run it with Nos on Web Simulator
5)   Write concurret program (run under Nos) to
   5.1)   Synchronise three processes
   5.2)   A central post office, send/receive messages from N processes
6)   Write a program for NPU to perform reduction (sum of an array)
7)   Cache design
     Perform experiment on Cache design with the given trace.
      Large trace:   
             This is a trace of a compiler, Som v. 4.1, compiles itself. See this page for the detail about the compiler
              http://www.cp.eng.chula.ac.th/~piak/project/som/index.htm
              The trace file is trx.zip (5 Mbytes). When unzip it is ~100Mbytes.
              each line contains an address xxx {r,w} r is read w is write
              data is at 0..371192
               instruction is at 400000..410873
               total number of instruction executed is 4520058
               total number of data access is 1044647.
8)  Term paper:  Write "Future of Graphic Processing Units", to answer the following questions:
  8.1)  What is the state of the art of GPU? 
  8.2)  What is the bottleneck of using GPU as general purpose computing devices?
  8.3)  What will be the balance between CPU and GPU in the future?
Prepare 10 minutes presentation of your study.

Tools

Logic Works 5   (get it from here,  11 Mbytes)    Just unzip it, no need to "install".
S23 assembly language
Rz language and its compiler
assembler for s23  as23-1.zip
rz36 with interrupt and Nos support  include executable rz36 and as23:  rz36-2.zip
NPU simulator, assembler  npsim4.zip
Code for Cache simulation to be used in Cache design assignment.  cache.zip
Transistor level simulation of an antique CPU.  6502 is used in the iconic Apple II machine.
    http://visual6502.org/JSSim/index.html

Reference

Exaflop machine    The full report    TR-2008-13.pdf  (3 Mb)
The Opportunities and Challenges of Exascale Computing, (pdf 2 Mb) US Department of Energy, Fall 2010
Kogge, P. "The tops in flops", IEEE spectrum, vol.48, issue 2, Feb 2011, pp.48-54,
    Digital Object Identifier : 10.1109/MSPEC.2011.5693074


last update  27 Feb 2014