S3.0  Multicore processor

S3.0 is a multicore processor with S2.1 instruction set.  Each core has its own "program" memory but all cores share "data" memory.  So, when fetching instructions, there is no memory access conflict (as each core has its own program memory).  Because data memory is shared, the conflict access can occurs.  However, initially, we assume no data memory access conflict. 

All cores have their own hard/soft interrupt. The interrupt vector of core N (N = 0..maxcore) of interrupt K (K = 0..3) is at M[1000 + 4*N + K].

When program multicore processors, we write assembly code for all cores in one file.  So, it is similar to write a single core program.  A special instruction, "cid r1" (core id), returns the core number. This instruction is used to differentiate an individual core so that we can assign different cores to execute different part of code.  Here is an example:

:main
    cid r3        ; core number in r3
    eq r2 r3 #0
    jt r2 program1
    jmp program2

:program1         ; this is run by core 0
    ....         

:program2         ; this is run by core 1

Coordinate multicore

To make multicore work collaboratively we need semaphore (similar to single core) and the new all core "sync" instruction.  All core sync will synchronise every core.  Two instructions help synchronise pair of core, waitx/sigx  (imitate semaphore).

How to block the current process.  A processor needs to stop itself, then "wake up" by another process.  When a processor stops, it can only be wake up by the external signal.  A new instruction "waitx" puts the core into a wait state. It can be waken up when another core sends "intercore signal" by the instruction "sigx #c" to it.

Here is an example how to synchronise two cores.  Count1 runs on core 0 and Count1 runs on core 1.  Each loop of Count1 waits for external signal.  The signal comes from Count2 "sigx #0".  So, loop of Count1 is synchronise with loop of Count2 (each prints its number alternatingly).  We put in some delay in Count2 to make sure that Count1 reaches "waitx" before Count2 executes "sigx #0".

.code 0
    cid r3
    eq r2 r3 #0
    jt r2 count1
    jmp count2

If you run the above program, the output looks like this:

C:\s30\test>sim30 -2 count-sigx.obj
2 cores, load program, last address 30
>g
1 +11 2 +12 3 +13 4 +14 5 +15 core 0 stop, clock 54
+16 +17 +18 +19 +20 core 1 stop, clock 101
>

What will happen if "sigx" is send to core that is not in "waitx"?  The signal will be just ignored.  We have to be careful not to send "sigx" to the core that is already stop as it will continue to execute the unknown instruction.

Process synchronisation

To perform all-core synchronisation,  each core executes "sync" instruction and send itself into wait state. When all cores execute "sync", every core will be wake up to continue. If only some core need to be sync, it is better to use "waitx/sigx".   Here is an example:

  p1()                        p2()
     i = 0                       i = 10
     while i < 5                 while i < 20
         print i                     print i
         i++                         i++
     sync                        sync
     stop                        stop

p1 runs loop to print 0..4.  p2 runs loop to print 10...19.  p1 reaches the end faster than p2 but it waits there. p2 catches up at "sync", then both cores proceed to stop. 

The implementation of sync uses "runflag[core]" to control the start/stop of cores.  Here is the pseudo code (NC number of core, the current core is k):

Using the simulator (sim30)

The simulator has the following commands:

a - show all cores
g - go
t - single step
b ads - set breakpoint
c n - focus core n
s [rn,mn,pc] v - set
d ads n - dump
r - show register
q - quit
h - help

Example programs

Summary

There are new instructions to support collaboration of multicore.  All of them must be real instructions, they can not be written as sequence of other instructions as they control start/stop of cores.

Update for s30-6 package

Tools