Specification of CPU3
A full description is contained in the lab sheet no 5. This document
will give you some addition information and hint on implementation.
Errata
ID instruction
Byte ordering
I/O port
Hint for implementation
Errata
Some errata in the lab sheet :
about addressing mode :
INA, OUT, STX has no immediate addressing mode.
about op code :
-
the opcode 001011 is not defined (between POP and INA)
-
ROR has the op code 011111 (31 in decimal )
-
ID instruction has the opcode 100000
(32 decimal)
when ID is executed it will place 8-bit student id into AC. (least
significant byte).
Byte ordering
The byte-ordering of 16-bit quantity needs clarification. The
cpu3 is a Big Endian machine, it means that the byte-order is most
significant byte first (HI byte). For example, LDX #256 , the operand
is a 16-bit quantity, will be ordered " 01 00 " hex in the memory.
When pushing a 16-bit quantity into a stack the order will be LO byte,
then HI byte. So that the order of byte in the stack segment and
code segment will be similar. Therefore, when poping 16-bit quantity,
pop HI byte first then LO byte.
I/O port
Input, Output Ports are logical, this means that the port number 0..7 is
for a programmer to use, the actual whereabout this port will be depends
on your physical design. Hence, Input port 0 and Output port 0 can
be physically different even if they have the same port number.
Hint for implementation
If you find the project is overwhelm, try to do the easier subset of the
design first. I recommend the following :
-
Ignore interrupt. Interrupt is asynchronous which make it difficult to
get it right.
-
Don't do Carry bit. Carry involves the overflow of AC unlike N and
Z. N can be implement easily by checking the most significant
bit (bit 7). Z is or-ing of all bits.
-
Ignore 16-bit quantity : the X register and all its instructions : LDX,
STX, INX, DEX, TSX.
-
Once you don't have X register, you also ignore index addressing mode.
-
Ignore ROL, ROR. It is tricky to do these "rotate through carry".
One good source of information how each instruction can be implemented
please look at the source code (in C language thereof) of the simulator
for cpu3. You can get lab 5 (scan keyboard and display) to work without
any indexing mode and only small subset of instruction set. Try to
write the program for lab 5 first to see which instruction is required.
If everything fails please contact me promptly before the final exam.