Design of a two-phase clocked control unit for performance enhancement of a stack processor

Alongkot Burutarchanai and Prabhas Chongstitvatana
Department of computer engineering
Chulalongkorn university

Proc. of National Conference of Computer Science and Engineering 2004, pp.114-119.


This work presents a design of the control unit for a 16-bit stack processor in embedded systems.  The design consideration includes efficient use of resources, simple data path and suitable instruction set.  The design emphasises simplicity to enable its synthesis on a real device.  The experiment is carried out on a FPGA device.  The prototype works correctly.  It consumes 5,413 equivalent gates and operates at the maximum frequency 46 MHz.