4B control unit


The 4B instruction set

ldx ads
ldy ads
stx ads
jmp ads
jt ads
jf ads

xop

add
sub
inc
dec
and
or
eq
eqz

We will consider a conceptually interesting and simple type of control unit, microprogrammed control unit.  It is almost like having a small computer as a control unit.

Microprogram control unit


Here are the elements in 4B:

data path

data memory
register x, y
alu, flag
mux at input register x

control path

program memory
instruction register
program counter
mux at input pc

Here are the control signals

data memory:  mread, mwrite
reg x,y : lx, ly  
mux at x:  sx_m, sx_alu  (select memory/alu)
alu:   alu_op  (add, sub ...)

program memory:  pgmread
ir: lir
pc: lpc
mux pc: sp_ads, sp_nxt (load ads, pc+1)

The microprogrammed control unit has all these control signals and the control bits for sequencing the microprogram itself.  They are:

fetch    goto the beginning of microprogram
next     next step
decode   goto the step corresponding to opcode

We will later explain how these microprogram control bits work.

Now let us start with the microprogram sequence that fetch an instruction from the program memory.

Timing

A cycle consists of a cycle of master clock. The first positive edge is denoted e1, the first negative edge is denoted e2.

fetch an instruction

pgmread e1, lir e2, next
sp_nxt e1, lpc e2, decode


each instruction

ldx:  mread e1, sx_m e1, lx e2, fetch
ldy:  mread e1, ly e2, fetch
stx:  mwrite e1, fetch
jmp:  sp_ads e1, lpc e2, fetch
jt:   sp_ads e1, ift_lpc e2, fetch
jf:   sp_ads e1, iff_lpc e2, fetch


xop

add:  alu_op e1, lx e2, fetch
...
eq:   alu_op e1, update_flag, fetch
eqz:  alu_op e1, update_flag, fetch


Let us discuss the holding time for the first half duration of the master clock.  At e2, the input of all registers are valid and we trigger loading the register.  It is assumed that the signals such as mread, alu_op are valid upto this point in time (e1 to e2).  To make sure there is no glitch, we should hold them a bit longer (until after e2).  To do that we use delay.

master clock (mclk)
clk2 = ~mclk

e2 = pos edge of clk2

clk1 = mclk + delay

mread, alu_op etc.  are  clk1

Finally, we discuss the sequencing of microprogram itself.

The microprogram can be regarded as a big ROM.  The sequence of control comes from the microprogram counter (upc).  We control the sequence by three events: fetch, next, decode.

fetch:  clear upc (to zero, start at the beginning)
next:   goto next step
decode:  load upc with micro_address

The micro_address is the address of the microprogram in correspondent to the opcode of the 4B instruction.  There are two fields of an instruction: op, ads.  For the extended opcode the "ads" field indicate the type of operations. So, the micro_address is a ROM with the input of an instruction and the output is the address of sequence of microprogram corresponded to that instruction.

Timing of micro sequence

Three events to control the sequence of microprogram: fetch, next, decode. When that should happen?   We can let it runs next step by default. In this case, the decode/fetch will happen at e1 of the next step.  It is a bit slow though.  If we want to interleave decode/fetch (so that it does not take another step), we can do it after e2.  To have a quarter duration, let denote it e3, we need to double the master clock.

masterx2  = double master clock

mpgm clk = ~master and ~masterx2

e3 = pos edge of mpgm clk

There are still some small details you have to think carefully, the conditional jump of micro operation:  ift_lpc, iff_lpc.  The lpc depends on the state of flag.

end

last update 23 Sept 2021