ARM

32-bit data path
16 32-bit registers
all instructions have conditional

instruction format
cond:4 op:8 rn:4 rd:4 rot:4 imm:8
cond:4 op:8 rn:4 rd:4 shfim:5 shf:2 0:1 rm:4
cond:4 op:8 rn:4 rd:4 imm:12
cond:4 op:4 ads:24

conditional
EQ, NE         equal, not equal  
CS/HS, CC/LO   carry set, higher or same,
MI, PL         minus, plus
VS, VC         overflow, nooverflow
HI, LS         higher, lower or same
GE, LT, GT, LE  signed greater than ...
AL, NV         always, never

addressing mode

shifter operand 3 formats:
1) immediate rot:4 imm:8
rotate imm with even no. bit (0..30)  
2) register
3) shifted register shf:2 rm:4
reg operand is shifted: ASR, LSL, LSR, ROR, RRX
ex:  add r9 r5 r5 lsl #3

immediate offset    12-bit offset
register offset     rn +/- rm
scaled reg ofs      rn +/- rm shf #shfim
imm pre-indexed     rn +/- 12-bit offset
reg pre-indexed     rn +/- rm
scaled reg pre-idx  rn +/- rm shf #shfim
imm post-idx        rn +/- 12-bit offset
reg post-idx        rn +/- rm
scaled reg post-idx rn +/- rm shf #shfim

instruction set

load/store
LDR   load word
LDRB  load byte
LDRBT load byte with user mode
LDRT  load word with user mode
LDRH  load unsigned halfword
LDRSB load signed byte
LDRSH load signed halfword
LDM   load multiple (reg)
STR   store word
STRB  store byte
STRBT store byte with user mode
STRT  store word with user mode
STRH  store halfword
STM   store multiple (reg)

B   branch
BL  branch and link
BX  branch and exchange
MOV move (shift)
MVN move not
ADD add
ADC add with carry
SUB
SBC
RSB reverse subtract
RSC 
AND
EOR
ORR
XOR
BIC bit clear
CMP compare
CMN compare negated
TST test
TEQ test equivalence
MLA   multiply accumulate
MUL   multiply
SMLAL signed mul acc long
SMULL
UMLSL unsigned mul acc long
UMULL

Thumb

32-bit data path
8 32-bit registers
16-bit instructions

Thumb state is entered by ARM BX instruction.   Thumb allows compact code.

instruction format
op:5 im:5 rm:3 rd:3
op:7 rm:3 rn:3 rd:3
op:7 im:3 rn:3 rd:3
op:5 r:3 im:8
op:10 r1:3 r2:3
op:4 cond:4 ads:8
op:5 ads:11

addressing mode
immediate offset
register ofs
pc-relative
sp-relative

instruction set

load/store
LDR   load word
LDRB  load unsigned byte
LDRH  load unsigned halfword
LDM   load multiple
STR   store word
STRB  store unsigned byte
STRH  store unsigned halfword
STM   store multiple
POP   pop multiple
PUSH  push multiple

B   branch (cond)
BL  branch and link
BX  branch and exchange
MOV move
MVN move not
ADD add
ADC add with carry
SUB
SBC
NEG negate
AND
EOR
ORR
BIC bit clear
CMP compare
CMN compare negated
TST test
MUL multiply
LSL logical shift left
LSR logical shift right
ASR arithmetic shift right
ROR rotate right

Reference

Jaggar, D., (ed), Advanced RISC Machine architectural reference manual, Prentice hall, 1996.