S2 microsteps

opcode ld st jmp jal jr add sub mul div and or xor shl shr trap
addressing mode 
a absolute
d displacement
x index
i immediate

unique opcode names
lda	ld r1,temp
ldd	ld r1,10(r2)
ldx	ld r1,(r2+r3)
ldi	ld r1,#100
add	add r1,r2,r3
addi	add r1,#20
others are similar
sta std stx sub subi mul muli div divi and andi or ori xor xori
shl shr trap
(note: no sti, shli, shri)

instruction format
L-format	op:5 r1:5 ads:22
D-format	op:5 r1:5 r2:5 disp:17
X-format 	op:5 r1:5 r2:5 r3:5 xop:12

<FETCH>
MAR = PC
MDR = M[MAR]; PC = PC+1

<DECODE>
IR = MDR

<LDA>
MAR = IR:ADS
MDR = M[MAR]
R[IR:R1] = MDR

<LDD>
T = R[IR:R2] + IR:DISP
MAR = T
MDR = M[MAR]
R[IR:R1] = MDR

<LDX>
T = R[IR:R2] + R[IR:R3]
MAR = T
MDR = M[MAR]
R[IR:R1] = MDR

<LDI>
R[IR:R1] = IR:DISP

<STA>
MAR = IR:ADS
MDR = R[IR:R1]
M[MAR] = MDR

<STD>
T = R[IR:R2] + IR:DISP
MAR = T 
MDR = R[IR:R1]
M[MAR] = MDR

<STX>
T = R[IR:R2] + R[IR:R3]
MAR = T 
MDR = R[IR:R1]
M[MAR] = MDR

<JMP>
IF TESTCC(IR:R1) PC = IR:ADS

<JAL>
R[IR:R1] = PC
PC = IR:ADS

<JR>
PC = R[IR:R1]

<ADD>
T = R[IR:R2] + R[IR:R3]
R[IR:R1] = T

<ADDI>
T = R[IR:R2] + IR:DISP
R[IR:R1] = T

similary for SUB SUBI MUL MULI DIV DIVI AND ANDI OR ORI XOR XORI

<SHL>
T = SHIFLEFT(R[IR:R2])
R[IR:R1] = T

<SHR>
T = SHIFTRIGHT(R[IR:R2])
R[IR:R1] = T

<TRAP>
simulator dependent

timing 	clocks  (assume no wait memory)
lda	6
ldd	7
ldx	7
ldi	4
sta	6
std	7
stx	7
jmp	4
jal	5
jr	4
add	5
addi	5
. . .
shl	5
shr	5
trap	4