there are four interrupts: int0, int1, int2, int3
interrupt vector at M[1000-1003]
only one interrupt is accepted and it runs to completion. ***
priority: int0 > int1 > int2 > int3
int #n op x 31 24 software
interrupt
ei #n op x 31 25 enable
interrupt
di #n op x 31 26 disable
interrupt
reti op x 31 27
return from interrupt
wfi op x 31 28
sleep and wait for interrup
#n is in r2 field. It is 5-bit (0..31)
when interrupt occurs, it jumps to ISR with return address stored in r31. reti terminates ISR and restores PC from r31 and enable interrupt to let other ISR run. wfi puts the processor to sleep and wait for interrupt. When interrupt occurs, the processor jumps to ISR when it returns it will continue the next instruction followed wfi.
trap r1 #13 set timer0 range
trap r1 #14 set timer1 range
trap r1 #18 read port, r1 is port number
trap r1 #19 write port, r1 is port number
10 analog input (sine wave)
11 digital input (square wave)
12 random number input
13 master clock
input the
number of clock since the board reset
last update 31 Jan 2025