;;   s30 multicore
;;   show two cores counting with interrupt

;;   interrupt vector address
;;   core 0  M[1000]
;;   core 1  M[1001]


.symbol
	stop 	0
	print1	17
	print2	18
	count1	200
	count2	201

.code 0
	mv r1 #inc1
	st r1 1000
	mv r1 #inc2
	st r1 1001     ;; set intvec
	st r0 count1
	st r0 count2   ;; clear counter
	cid r3
	eq r2 r3 #0
	jt r2 main1
	jmp main2

;; ---------- core 0 ------------
:main1
	ei  
:loop1
	wfi
	ld r1 count1
	eq r2 r1 #10
	jf r2 loop1
	di
	trap stop

;; --- core0 isr -----

:inc1
	ld r3 count1
	mv r1 r3
	trap print1
	add r3 r3 #1
	st r3 count1
	reti

;; -------- core 1 --------------
:main2
	ei  
:loop2
	wfi
	ld r1 count2
	eq r2 r1 #10
	jf r2 loop2
	di
	trap stop

;; --------core1 isr ---------
:inc2
	ld r3 count2
	mv r1 r3
	trap print2
	add r3 r3 #1
	st r3 count2
	reti

.end