This is the third installment of a series of Byte.com columns that will explore the inner workings of Intel's new IA-64 architecture -- officially dubbed EPIC
(explicitly parallel instruction computing) -- and its first incarnation, the Merced microprocessor.
Now that Intel has at long last revealed the instruction set that will be used in its Merced and subsequent IA-64 microprocessors, the technical community is weighing in with its collective opinion. The initial reaction has been decidedly oxymoronic: Engineers are impressed, yet underwhelmed.
On the one hand, the unprecedented complexity of IA-64 proves Intel's designers don't shy away from a challenge. Indeed, they've shown real guts by ignoring all the naysayers and putting together a forward-looking architecture while grappling with the real-world compromises inherent in such a task.
The result, however, is a somewhat cobbled-together appearance. Since Intel started designing its 64-bit effort on a clean sheet of paper (sullied only by the requirements of upward X86 and PA-RISC compatibility), that's a bit of a disappointment. Rather, the architecture should be totally fresh and cleanly laid down in silicon -- the microprocessor equivalent of a magnificently balanced skyscraper.
Media Mania
When Intel unveiled news of the instruction set on May 26th, it was looking for some mileage in the mainstream press. Intel's public-relations machine regularly leaks information to the media like a drip coffee maker, in hopes of spouting steady streams of favorable stories.
This time, however, Intel's presentation (with the exception of the instruction set) was mostly a rehash of previously disclosed material, and it landed with a big thud. The gist of the message was: IA-64 is great, and Merced will be great, too. (Oh, and by the way, McKinley -- the follow-on to Merced -- will be better still.)
The technical documents Intel released, though, are significant, as they present the first important picture to be gleaned of IA-64. The instruction set, along with other details of the architecture, is detailed in two lengthy tomes (and several other related documents) you can download from Intel's FTP site.
>>>Instruction Observations
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