Reading List Computer Architecture 2002
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IEEE MICRO, Vol. 17, No. 2: MARCH/APRIL 1997, A Case for Intelligent
RAM, D. Patterson, T. Anderson, N. Cardwell, R. Fromm, pp. 34-44
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IEEE Computer, November 1998, "A new direction in computer architecture
research", C. Kozyrakis and D. Patterson, pp.24-32
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IEEE Micro, March/April 2000, Vector unit architecture for emotion synthesis,
Kunimatsu, A.; Ide, N.; Sato, T.; Endo, Y.; Murakami, H.; Kamei,
T.; Hirano, M.; Ishihara, F.; Tago, H.; Oka, M.; Ohba, A.; Yutaka, T.;
Okada, T.; Suzuoki, M, p.40
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IEEE Micro, March/April 1999, Implementing Neon: A 256-bit graphics accelerator,
McCormack, J.; McNamara, R.; Giano, C.; Jouppi, N.P.; Dutton, T.; Zurawski,
J.; Seiler, L.; Correll, K.,p. 58
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IEEE Micro, March/April 1999, IBM's deep blue chess grandmaster chips,
F. Hsu., p.70
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IEEE Micro, March/April 2000, Xtensa: a configurable and extensible processor,
Gonzalez, R.E., p.60
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IEEE micro July/August 2001, The challenges of wearable computing: Part
1 Starner, T. pp. 44-52, part 2, pp. 53-67.
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IEEE micro May/June 2001, wearARM modular, low-power computing core. Lukow-icz,
P., et al., pp. 16-28
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IEEE micro Jan/Feb 2001, ternary CAM, fast routing lookups and packet class.
Shah, D., et al., pp. 36-47
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IEEE Micro Sept.-Oct. 2001 Volume: 21 Issue: 5 , A self-repairing execution
unit for microprogrammed processors, Benso, A.; Chiusano, S.; Prinetto,
P. Politecnico di Torino, pp. 16 - 27
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IEEE Micro March/April 2001, The iflow address processor O'Connor, M.;
Gomez, C.A. pp. 16 -23
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IEEE Micro March/April 2001, Toward quantum computation: a five-qubit quantum
processor, Steffen, M.; Lieven, M.K.; Vandersypen; Chuang, I.L. pp. 24
-34
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IEEE Micro Nov/Dec 2000, Power-aware microarchitecture: design and modeling
challenges for next-generation microprocessors, Brooks, D.M.; Bose, P.;
Schuster, S.E.; Jacobson, H.; Kudva, P.N.; Buyuktosunoglu, A.; Wellman,
J.; Zyuban, V.; Gupta, M.; Cook, P.W. pp. 26 -44
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IEEE Micro July/August 2000, Introducing the FR500 embedded microprocessor,
Suga, A.; Matsunami, K. pp. 21 -27
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IEEE Micro July/August 2000, SH-5: the 64 bit superH architecture, Biswas,
P.; Hasegawa, A.; Mandaville, S.; Debbage, M.; Sturges, A.; Arakawa, F.;
Saito, Y.; Uchiyama, K. pp. 28 -39
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IEEE Micro, July/Aug 1999, Deep-submicron microprocessor design issues,
Flynn, M.J.; Hung, P.; Rudd, K.W., p. 11
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IEEE Micro, July/Aug 1999, High-performance RISC microprocessors, Choquette,
J.; Gupta, M.; McCarthy, D.; Veenstra, J..p.48
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IEEE Micro, May/June 1999, UltraSPARC-III: Designing Third-Generation 64-Bit
Performance, Horel, T.; Lauterbach, G.. p. 73
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IEEE Micro, March/April 1999,IBM's S/390 G5 microprocessor design, Siegel,
T.J.; Averill, R.M.; Check, M.A.; Giamei, B.C.; Krumm, B.W.; Krygowski,
C.A.; Lee, W.H.; Liptay, J.S.; MacDougall, J.D.; McPherson, T.J.;
Navarro, J.A.; Schwarz, E.M.; Shum, K.; Webb, C.F. p. 12
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IEEE MICRO, Vol. 17, No. 5: SEPTEMBER/OCTOBER 1997, Two Fast
and High-Associativity Cache Schemes , C. Zhang, X. Zhang, Y. Yan, pp.
40-49
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Lx: a technology platform for customizable VLIW embedded processing,
P. Faraboschi, G. Brown, J. A. Fisher, G, Desoli and F, Homewood,
27th Annual International Symposium on Computer architecture June
10 - 14, 2000, Vancouver Canada, pp. 203 - 213