S2 microsteps (modified)

Microsteps
Timing

In order to protect flags (Z,S,C) from being affected by load/store instructions, I add one adder to perform effective address calculation. Inputs of this adder are the same as inputs of ALU. The output of this adder drives data bus directly. Therefore it can transfer the address to MAR without having to go through T, which will save one clock compare to the original S2 microsteps.

The microsteps that are affected are: ldd, ldx, std, stx

Microsteps

<LDD>
MAR = adder(R[IR:R2], IR:DISP)
MDR = M[MAR]
R[IR:R1] = MDR

<LDX>
MAR = adder(R[IR:R2], R[IR:R3])
MDR = M[MAR]
R[IR:R1] = MDR

<STD>
MAR = adder(R[IR:R2], IR:DISP)
MDR = R[IR:R1]
M[MAR] = MDR

<STX>
MAR = adder(R[IR:R2], R[IR:R3])
MDR = R[IR:R1]
M[MAR] = MDR

Timing

timing clocks (assume no wait memory)
* modified

lda     6
ldd     6 *
ldx     6 *
ldi     4
sta     6
std     6 *
stx     6 *
jmp taken 5
jmp not taken 4
jal     5
jr      4
add     5
addi    5
. . .
shl     5
shr     5
trap    4