In order to protect flags (Z,S,C) from being affected by load/store instructions, I add one adder to perform effective address calculation. Inputs of this adder are the same as inputs of ALU. The output of this adder drives data bus directly. Therefore it can transfer the address to MAR without having to go through T. The microsteps that are affected are: ldd, ldx, std, stx
<FETCH>
MAR = PC
MDR = M[MAR]; PC = PC+1
<DECODE>
IR = MDR
<EXECUTE>
jump to individual instruction
determined by opcode field IR:OP
<LDD>
MAR = adder(R[IR:R2], IR:DISP)
MDR = M[MAR]
R[IR:R1] = MDR
<LDX>
MAR = adder(R[IR:R2], R[IR:R3])
MDR = M[MAR]
R[IR:R1] = MDR
<LDI>
R[IR:R1] = IR:DISP
<STA>
MAR = IR:ADS
MDR = R[IR:R1]
M[MAR] = MDR
<STD>
MAR = adder(R[IR:R2], IR:DISP)
MDR = R[IR:R1]
M[MAR] = MDR
<STX>
MAR = adder(R[IR:R2], R[IR:R3])
MDR = R[IR:R1]
M[MAR] = MDR
<JMP>
IF TESTCC(IR:R1) // jump not taken
PC = IR:ADS // jump taken
<JAL>
R[IR:R1] = PC
PC = IR:ADS
<JR>
PC = R[IR:R1]
<ADD>
T = R[IR:R2] + R[IR:R3]
R[IR:R1] = T
<ADDI>
T = R[IR:R2] + IR:DISP
R[IR:R1] = T
similary for SUB SUBI MUL MULI DIV DIVI AND ANDI OR ORI XOR XORI
<SHL>
T = SHIFLEFT(R[IR:R2])
R[IR:R1] = T
<SHR>
T = SHIFTRIGHT(R[IR:R2])
R[IR:R1] = T
<TRAP>
simulator dependent
lda 6
ldd 6
ldx 6
ldi 4
sta 6
std 6
stx 6
jmp taken 5
jmp not taken 4
jal 5
jr 4
add 5
addi 5
. . .
shl 5
shr 5
trap 4
last update 25 December 2002