S2 microsteps

opcode: ld st jmp jal jr add sub mul div and or xor shl shr trap
addressing mode: a absolute, d displacement, x index, i immediate

In order to protect flags (Z,S,C) from being affected by load/store instructions, I add one adder to perform effective address calculation.  Inputs of this adder are the same as inputs of ALU.  The output of this adder drives data bus directly.  Therefore it can transfer the address to MAR without having to go through T.  The microsteps that are affected are:  ldd, ldx, std, stx

unique opcode names

opcode     example of use
lda     ld r1,temp
ldd     ld r1,10(r2)
ldx     ld r1,(r2+r3)
ldi     ld r1,#100
add     add r1,r2,r3
addi    add r1,#20
. . .
others are similar
sta std stx sub subi mul muli div divi and andi or ori xor xori
(note: no sti, shli, shri)

instruction format

L-format  op:5 r1:5 ads:22
D-format  op:5 r1:5 r2:5 disp:17
X-format  op:5 r1:5 r2:5 r3:5 xop:12

Microsteps

run -> loop (
    <FETCH>
    <DECODE>
    <EXECUTE>
  )

<FETCH>
MAR = PC
MDR = M[MAR]; PC = PC+1

<DECODE>
IR = MDR

<EXECUTE>
jump to individual instruction
determined by opcode field IR:OP

Individual instruction

<LDA>
MAR = IR:ADS
MDR = M[MAR]
R[IR:R1] = MDR

<LDD>
MAR = adder(R[IR:R2], IR:DISP)
MDR = M[MAR]
R[IR:R1] = MDR

<LDX>
MAR = adder(R[IR:R2], R[IR:R3])
MDR = M[MAR]
R[IR:R1] = MDR

<LDI>
R[IR:R1] = IR:DISP

<STA>
MAR = IR:ADS
MDR = R[IR:R1]
M[MAR] = MDR

<STD>
MAR = adder(R[IR:R2], IR:DISP)
MDR = R[IR:R1]
M[MAR] = MDR

<STX>
MAR = adder(R[IR:R2], R[IR:R3])
MDR = R[IR:R1]
M[MAR] = MDR

<JMP>
IF TESTCC(IR:R1) // jump not taken
  PC = IR:ADS    // jump taken

<JAL>
R[IR:R1] = PC
PC = IR:ADS

<JR>
PC = R[IR:R1]

<ADD>
T = R[IR:R2] + R[IR:R3]
R[IR:R1] = T

<ADDI>
T = R[IR:R2] + IR:DISP
R[IR:R1] = T

similary for SUB SUBI MUL MULI DIV DIVI AND ANDI OR ORI XOR XORI

<SHL>
T = SHIFLEFT(R[IR:R2])
R[IR:R1] = T

<SHR>
T = SHIFTRIGHT(R[IR:R2])
R[IR:R1] = T

<TRAP>
simulator dependent

Timing

    timing  clocks  (assume no wait memory)
lda     6
ldd     6
ldx     6
ldi     4
sta     6
std     6
stx     6
jmp taken 5
jmp not taken 4
jal     5
jr      4
add     5
addi    5
. . .
shl     5
shr     5
trap    4


last update  25 December 2002