Syllabus

2110793 Advanced topic in digital systems

Prabhas Chongstitvatana

Description

To present the state of the art in the processor design. The topic covers preliminaries and performance driven design. I assume that students already familiar themselves with at least one or two subjects in computer organisation and hardware design. The knowledge of compilation technology is not required. We will discuss instruction set design, instruction level parallelism and cache memory design.

The course is divided into three parts: lecture, work examples and research materials. The first part will be normal lectures with assignments. I expect students to hand-in works every week. This part is a kick start to get yourself into the subject (after long years away from classes !). The second part is the "hand-on". I will emphasise simulation of a working processor at the instruction set level, including the control unit and pipeline. The final part will be conducted based on materials from research journals. I am looking into Intel Itanium architecture and low power design.

The emphasise on this semester (2nd semester 2002) will be on the relationship between high level language and instruction set architecture. We will experiment with compiling a high level language into a user defined ISA and measure the effect of the ISA on performance.

Behavioural objectives

1. students can analyse and evaluate the instruction set level of a computer
2. students can design and modify an instruction set
3. students can evaluate the current architecture
4. students can comment on the future architecture

Topic by Week

Introduction to computer architecture: the dataflow model and its sequentialisation, Von Neumann architecture.
Preliminaries: Discussion on instruction set design, performance metric.
Control unit
Microprogramming
S2 (a simple typical 32-bit processor)
Code generation (relationships between HLL, compiler and ISA)
Pipelining
Superscalar
VLIW
Memory system design
Speculative execution: Itanium processor
Future architecture: IRAM RAW
Low power design
Summary of the topic

Text

P. Chongstitvatana, "Computer architecture: a synthesis", 2000.
H. Stone, "High-performance computer architecture", 3 ed, Addison-Wesley publishing, 1993.
J. Hennessy and D. Patterson, "Computer architecture : a quantitative approach", 2 ed, Morgan Kaufmann P, 1996.
W. Stalling, "Computer organisation", 4ed., Prentice-hall, 1996. (undergrad level text)
Additional materials will be hand-out as needed.

Assessment

weekly homework   10%
midterm project   30%
final project     20%
final exam        40%