However, both predication and speculation are essentially shielded from the user. Instead, Merced's compiler decides when, where, and how to move code around.
Indeed, the actual instructions that execute on Merced will be so many generations removed from the original high-level language programming that debugging itself will become a different kind of challenge.
Thus, the chip itself has to serve as its own logic analyzer. To that end, Merced includes a full complement of performance-monitoring registers. These registers keep a running count of, for example, instructions per second and cache misses. The registers can be monitored in real time without hardware slowdown, without affecting the actual execution of the code.
Delivery Past Due
One thing Intel did not answer at its instruction-set unveiling was the big question on everyone's mind: When will samples be ready? Intel had pledged Merced would sample in the middle of this year. Now it says samples will come in the next few months. But Intel couldn't be pinned down further, even though it continues to promise production-quantity shipments in mid-2000.
For now, it's looking like Intel has boxed itself into a corner. Manuals will take it only so far. Soon, the company will have to show some silicon, or else address a rising chorus of industry rumors that McKinley (Merced's successor) will, in fact, be the first IA-64 processor to be used in quantity.
Yet, regardless of which chip hits first, the manuals corroborate what I've been saying all along about the unprecedented complexity of IA-64. Hardware-wise, things will be fine; it's software that's the key. The architecture will live or die on its compilers. 
Alexander Wolfe was trained as an electrical engineer and has covered the computer industry for the past 15 years. He is managing editor of computers and communications at Electronic Engineering Times.
BYTE Categories
