List of Papers
How to do a paper
Due date is 25th September 2000
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1997 IEEE COMPUTER, Vol. 30, No. 5: MAY 1997, pp. 71-81, Branch
Effect Reduction Techniques, Augustus K. Uht, Vijay Sindagi, Sajee Somanathan
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1997 IEEE COMPUTER, Vol. 30, No. 11: NOVEMBER 1997, pp. 67-76,
Asynchronous Processor Survey, Tony Werner, Venkatesh Akella
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1997 IEEE COMPUTER, Vol. 30, No. 12: DECEMBER 1997, pp. 63-69,
Compilers for Instruction-Level Parallelism, Michael Schlansker, Thomas
M. Conte, James Dehnert, Kemal Ebcioglu
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1997 IEEE MICRO, Vol. 17, No. 2: MARCH/APRIL 1997, pp. 34-44,
A Case for Intelligent RAM, David Patterson, Thomas Anderson, Neal Cardwell,
Richard Fromm
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1997 IEEE MICRO, Vol. 17, No. 2: MARCH/APRIL 1997, pp. 45-53,
picoJava-I: The Java Virtual Machine in Hardware, J. Michael O'Connor,
Marc Tremblay
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1997 IEEE MICRO, Vol. 17, No. 3: MAY/JUNE 1997, pp. 36-43,
Compiling Java Just in Time, Timothy Cramer, Richard Friedman, Terrence
Miller, David Seberger, Robert Wilson, Mario Wolczko
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1997 IEEE MICRO, Vol. 17, No. 5: SEPTEMBER/OCTOBER 1997, pp.
12-19, Simultaneous Multithreading: A Platform for Next-Generation Processors
, Susan J. Eggers, Joel S. Emer, Henry M. Levy
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1997 IEEE MICRO, Vol. 17, No. 5: SEPTEMBER/OCTOBER 1997, pp.
20-27, Exploiting Instruction- and Data-Level Parallelism , Roger Espasa,
Mateo Valero
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1997 IEEE MICRO, Vol. 17, No. 5: SEPTEMBER/OCTOBER 1997, pp.
40-49, Two Fast and High-Associativity Cache Schemes , Chenxi Zhang, Xiaodong
Zhang, Yong Yan
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1997 IEEE MICRO, Vol. 17, No. 6: NOVEMBER/DECEMBER 1997, pp.
18-28, Direct Rambus Technology: The New Main Memory Standard , Richard
Crisp
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1997 IEEE MICRO, Vol. 17, No. 6: NOVEMBER/DECEMBER 1997, pp.
55-62, Limited Bandwidth to Affect Processor Design , Doug Burger, James
R. Goodman, Alain Kägi
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1997 IEEE MICRO, Vol. 17, No. 5: SEPT/OCT 1997, pp. 12-19, Simultaneous
Multithreading: A Platform for Next-generation Processors, Susan Eggers,
Joel Emer, Henry Levy, Jack Lo, Rebecca Stamm, and Dean Tullsen
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IEEE Computer, November 1998, pp.24-32, "A new direction in computre architecture
research", C. Kozyrakis and D. Patterson.
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IEEE Micro, March/April 2000, Vector unit architecture for emotion synthesis,
Kunimatsu, A.; Ide, N.; Sato, T.; Endo, Y.; Murakami, H.; Kamei, T.; Hirano,
M.; Ishihara, F.; Tago, H.; Oka, M.; Ohba, A.; Yutaka, T.; Okada, T.; Suzuoki,
M, p.40
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IEEE Micro, March/April 2000, The MAP1000A VLIW mediaprocessor, Basoglu,
C.; Woobin Lee; O'Donnell, J.S., p.48
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IEEE Micro, March/April 2000, Xtensa: a configurable and extensible processor,
Gonzalez, R.E., p.60
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IEEE Micro, Jan/Feb 2000, Cache memory design for internet processors,
Chiueh, T.; Pradhan, P., p.28
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IEEE Micro, Jan/Feb 2000, The tigerSHARC DSP architecture, Fridman,
J.; Greenfield, Z.,p 66
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IEEE Micro, Nov/Dec 1999, Sega dreamcast: Creating a unified entertainment
world,Shiro Hagiwara, Ian Oliver., p.29
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IEEE Micro, Sept/Oct 1999, MASSC: A Generic Architecture For Multiapplication
Smart Cards, Jean-Pierre Tual.p. 52
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IEEE Micro, July/Aug 1999, Deep-submicron microprocessor design issues,
Flynn, M.J.; Hung, P.; Rudd, K.W., p. 11
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IEEE Micro, July/Aug 1999, Micro-RISC architecture for the wireless market,
Gonzales, D.R.. p.30
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IEEE Micro, July/Aug 1999, The D30V/MPEG multimedia processor, Takata,
H.; Watanabe, T.; Nakajima, T.; Takagaki, T.; Sato, H.; Mohri, A.; Yamada,
A.; Kanamoto, T.; Matsuda, Y.; Iwade, S.; Horiba, Y..p. 38
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IEEE Micro, July/Aug 1999, High-performance RISC microprocessors, Choquette,
J.; Gupta, M.; McCarthy, D.; Veenstra, J..p.48
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IEEE Micro, May/June 1999, Performance analysis and validation of the picojava
processor, Hangal, S.; O'Connor, M.. p. 66
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IEEE Micro, May/June 1999, UltraSPARC-III: Designing Third-Generation 64-Bit
Performance, Horel, T.; Lauterbach, G.. p. 73
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IEEE Micro, March/April 1999,IBM's S/390 G5 microprocessor design, Siegel,
T.J.; Averill, R.M.; Check, M.A.; Giamei, B.C.; Krumm, B.W.; Krygowski,
C.A.; Lee, W.H.; Liptay, J.S.; MacDougall, J.D.; McPherson, T.J.; Navarro,
J.A.; Schwarz, E.M.; Shum, K.; Webb, C.F.p. 12
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IEEE Micro, March/April 1999, The EMU10K1 digital audio processor, Savell,
T.C.,p.49
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IEEE Micro, March/April 1999, Implementing Neon: A 256-bit graphics accelerator,
McCormack, J.; McNamara, R.; Giano, C.; Jouppi, N.P.; Dutton, T.; Zurawski,
J.; Seiler, L.; Correll, K.,p. 58
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IEEE Micro, March/April 1999, IBM's deep blue chess grandmaster chips,
Feng-hsiung Hsu., p.70