Computer Architecture
Prabhas Chongstitvatana
Department of Computer Engineering
Chulalongkorn University
tel 218-6982 (direct), 218-6956 (secretary)
fax 218-6955
email prabhas@chula.ac.th
URL www.cp.eng.chula.ac.th/faculty/pjw
Scope : This class is supposed to be the SECOND class in
computer architecture. I assume prior exposure
to the basic material in computer architecture, either as the subject
in microprocessor or computer
organisation. The topics are as follows : Performance metrics,
central processing unit, control unit,
microprogramming, instruction level parallelism : pipeline, superscalar;
memory system, disk array, evolution
of architecture, future architecture.
Text :
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W. Stalling, "Computer organisation", 4ed., Prentice-hall, 1996.
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J. Hennessy and D. Patterson, "Computer architecture : a quantitative approach",
2 ed, Morgan Kaufmann Pub., 1996.
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H. Stone, "High-performance computer architecture", 3 edition, Addison-Wesley
publishing, 1993.
-
Additional materials will be hand-out as needed.
Approach : Students progress through a series of "computer
architecture design", starting from a basic machine and add performance
enhancements, i.e. pipeline, multi functional units etc. The design
is excercised by simulation at instruction level. There will be one
design assignment toward the middle of the semester. The selected
design will be presented to the class. Toward the end of the course,
future architecture will be discussed. Students will be assigned reading
materials from research journals. Students must hand in reports based
on their researches on those materials.
Weekly schedule
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Review of the basics of computer architecture
-
Performance metrics
-
Hypothetical processor design
-
Control unit
-
Microprogramming
-
Pipeline design techniques 1
-
Pipeline design techniques 2
-
Super scalar design 1
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Super scalar design 2
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Memory system design
-
Presentation of the students' design
-
Vector computers 1
-
Vector computers 2
-
Discussion on future architecture 1
-
Discussion on future architecture 2
Class work is composed of one design and measurement (using simulation)
of a computer around week 10. The selected papers will be presented
to the class by the authors. The discussion on future architecture
will be based on the assigned reading of the articles in the research journals
(mainly IEEE trans.) which students have to submit written reports.
Final exam. will be a 3-hour written exam.
Assessment
midterm
20
final
30
design
30
report
20