VLIW
| Mem Ref 1 | Mem Ref 2 | FP op 1 | FP op 2 | Int op / Branch |
| LD F0,0(R1) | LD F6,-8(R1) | |||
| LD F10,-16(R1) | LD F14,-24(R1) | |||
| LD F18,-32(R1) | LD F22,-40(R1) | ADD F4,F0,F2 | ADD F8,F6,F2 | |
| LD F26,-48(R1) | ADD F12,F10,F2 | ADD F16,F14,F2 | ||
| ADD F20,F18,F2 | ADD F24,F22,F2 | |||
| SD 0(R1),F4 | SD -8(R1),F8 | ADDF28,F26,F2 | ||
| SD –16(R1),F12 | SD –24(R1), F16 | |||
| SD –32(R1), F20 | SD –40(R1),F24 | SUBI R1,R1,#56 | ||
| SD 8(R1), F28 | BNEZ R1,LOOP |