instruction level parallelism

execution time =
   number of instruction executed x
   cycle per instruction x
   clock speed (GHz)

number of instruction executed
   depends on "instruction set" and benchmark 
   programs

cycle per instruction
   depends on "micro architecture design"
   or how the processor is organised inside
   the chip

clock speed
   depends on fabrication technology of
   the microchip   (nano meter) 
   (generation of chip technology)