2110362 Microprocessor Int. Laboratory

Memory Interface Module

Objective :   Design and build a memory interface module to connect with a 32K x 8 bit RAM.  Test that you can read and write that RAM properly.

Introduction

R1 chip is connected to a memory via MDR, MAR registers.  The steps for reading/writing a word  ( 8-bit ) from/to memory are :

memread :
MAR = ads
MDR = M[MAR]

memwrite :
MAR = ads
MDR = data
M[MAR] = MDR

MAR is a normal latch that stores value from DATA BUS.  MDR is more complicate as it has to store "both ways"  between DATA BUS and MEMORY.   We have to understand memory interface timing first.  (See memory data sheet )

Memory chip has address bus, bi-directional data bus and three controls : CS (chip select), WE (write enable)  and  OE (output enable).  We choose to control writing via WE and reading via OE.  As we may use only one memory module, CS will be enable all the time. 

The timing that we must consider are :
Read cycle 
tRC  read cycle time 
tAA   address access time
tOE  output enable to output valid
Write cycle
tWC  write cycle time
tWP  write pulse width
tAS    address set up time
tDW  data set up time
Note that tAS + tDW must be less than our write pulse control signal.


Memory Interface

We will define four control signals :  WMDR, RMDR, WMEM, RMEM  as write/read MDR, write/read MEMORY respectively.

WMDR	BUS to MDR
RMDR    MDR to BUS
WMEM   MDR to MEM
RMEM    MEM to MDR

Therefore to read a word from memory :
WMAR  set up address, RMEM  read memory to mdr.
To write a word to memory (assume data to write is already in MDR by WMDR)
WMAR  set up address, WMEM  write to memory.

MDR

The MDR must be bi-directional  hence we use four buffers to direct the bus and memory : FROMMEM, TOMEM, FROMBUS, TOBUS and a latch MDRLATCH to store the value.

Example :   Write a value in X to the memory at location specified by Y register.

we can write the steps as :
MAR = Y
MDR = X
M[MAR] = MDR

the first cycle :  RY, WMAR
the second cycle :  RX, WMDR
the third cycle :  WMEM