Advanced topic in digital systems   2002

Prabhas Chongstitvatana
email me
office:  Engineering building 4, floor 18, room 13,  phone 02-218-6982

Previous lecture    2001  1999

What's new

24 December 2002    Code generation
25 December 2002    S2 tools v1.0      S2   How assembler work
2  January 2003        How to add new instructions
8  January 2003        Midterm project      RZ compiler tools kit explained (update)    RZ language
13 January 2003       CISC/RISC characterization
11 March 2003         Itanium     Final exam     Trace file   Trace-readme     source code of benchmark
                               Itanium ISA manual  (in Itanium page)

Syllabus

Announcement

Aim

To present the state of the art in the processor design.  The topic covers preliminaries and performance driven design.  I assume that students already familiar themselves with at least one or two subjects in computer organisation and hardware design.   We will discuss instruction set design, instruction level parallelism and cache memory design.

Topic by Week

  1. Introduction to computer architecture:  the dataflow model and its sequentialisation,  Von Neumann architecture.
  2. Preliminaries: Discussion on instruction set design, performance metric.
  3. Control unit
  4. Microprogramming
  5. S2 (a simple 32-bit processor)   S2 ISA microsteps
  6. Code generation  (relationships between HLL, compiler and ISA)
  7. Pipelining
  8. Superscalar
  9. VLIW
  10. Memory system design  Cache memory
  11. Virtual memory
  12. Speculative execution:  Itanium processor
  13. Presentation of research paper
  14. Summary of the topic

Assignments

  1. Study an instruction set of a processor of your own choice.
  2. Write an assembly language for  f(x) = ax^2 + bx + c
  3. Write a simple program in high level language and rewrite it in an assembly language
  4. Design a microprogram for the evaluation of f(x) = ax^2 + bx + c
  5. S1: write a S1 assembly program, hand assemble it and run it on S1 simulator.
  6. Use RZ S2 package to create a high level language program and compile and run on S2 simulator

Handout

RZ s2 document

Reading

R1 concurrent system
Intel Itanium
Example of RZ2 compiler session
How the assembler work
RZ compiler kit page
How to add new instructions
RZ language
CISC/RISC characterization

Tools

All programs have been tested to compile correctly under gcc (and lcc)
S1 simulator
S1 microprogram systems   the package
C compilers
Benchmark programs in C
 

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