2110793  Advanced Topic in Digital Systems  Part 1    1999

What's new
21 June  SS VLIW Pentium Bug (pp 30-35)
           Current Microprocessors (including IA64)
28 June Evolution of architecture
            C. Kozyrakis and D. Patterson, "A new direction in computre architecture
            research",  IEEE  Computer, November 1998, pp.24-32. (pdf)
           1B transistors processor
29 June  Project reports  (7 July adds more reports) Off-line until 9th August 1999
Scope  Instruction level parallelism

Approach  The lectures will give direction for students to probe further.  Students have to read assigned papers to broaden and deepen their knowledge.  One project will be issued.  Students will do the architectural exploration how the instruction level parallelism work.

Syllabus  3 weeks lecture followed by presentation of individual projects. Topics of lecture : Instruction level parallelism, Performance metrics, Pipelining, Classical method :  Scoreboard, Tomasulo, Modern processors.

Lecture

Projects   suggested ideas

Report  Off line until 9th August

  • S1 with branch prediction : heuristic tuning of branch prediction scheme, Wiwat Vatanawood.
  • 2 Stages pipeline of S1, Pichayothai Mahatthanapiwat
  • Reduction of CPI in a VLIW processor, Worasait Suwannik
  • Dynamic Scheduling with Tomasulo technique, Radchaporn Kienprasit
  • Two-level branch prediction, Dechanuchit Katunyataweetip
  • Minimize data hazard stalls by forwarding technique, Nuanwan Soonthornpaisaj
  • Improvement the S1p with branch prediction and 2-bit history branch target buffer, Nuttakorn Tubthong
  • Scoreboard technique with 2 ALUs, Sukree Sinthupinyo
    • Tools Reading

            VLIW  (the first two can be obtained from me)

    1. Fisher, J., Ellis, J., Ruttenberg, J. and Nicolau, A., "Parallel processing:  a smart compiler and a dumb machine", Proc. of the ACM SIGPLAN'84 Symp. on Compiler Construction, SIGPLAN notice vol. 19, no. 6, June 1984.
    2. Colwell, R., Hall, E., Joshi, C., Papworth, D., Rodman, P., Tornes, J., "Architecture and implementation of a VLIW supercomputer", IEEE Int Conf. ? , ref CH2916-5/90/0000/0910, pp. 910-919.
    3. How IA64 exposes intruction level parallelism, IEEE Computer (magazine), July 1998.
    4. Reading about current Microprocessors and Pentium Performance
    5. Future Architecture, IEEE Computer, September 1997.
    6. C. Kozyrakis and D. Patterson, "A new direction in computre architecture research",  IEEE     Computer, November 1998, pp.24-32. (pdf)
    Text
    1. H. Stone, "High-performance computer architecture", 3 ed, Addison-Wesley publishing, 1993.
    2. J. Hennessy and D. Patterson, "Computer architecture : a quantitative approach", 2 ed, Morgan Kaufmann Pub., 1996.
    3. W. Stalling, "Computer organisation", 4ed., Prentice-hall, 1996. (undergrad level text)
    4. Additional materials will be hand-out as needed.