Advanced topic in digital systems   2004

Prabhas Chongstitvatana
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office:  Engineering building 4, floor 18, room 13,  phone 02-218-6982
 

Previous lecture    2002     2001  1999

What's new

16 July 2004   Intro to comp arch,    ISA design,   control unit
20 Aug 2004   Midterm projects

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Syllabus

Announcement

11 June    the lecture room is   Wed. 1-2:30pm  3307, Fri  2:30-4pm  3206
20 Aug 2004   Midterm projects    hand-in 10 September 2004 in class

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Aim

To present the state of the art in the processor design.  The topic covers preliminaries and performance driven design.  I assume that students already familiar themselves with at least one or two subjects in computer organisation and hardware design.   We will discuss instruction set design, instruction level parallelism and cache memory design.
 

Topic by Week

   1. Introduction to computer architecture:  the dataflow model and its sequentialisation,  Von Neumann architecture.
   2. Preliminaries: Discussion on instruction set design, performance metric.
   3. Control unit, microprogramming
   4. S2 (a simple 32-bit processor), S2 ISA microsteps
   5. Code generation  (relationships between HLL, compiler and ISA)
   6. Pipelining, Superscalar, VLIW
   7. midterm project discussion
   8. Memory system design  Cache memory, virtual memory
   9. Speculative execution:  Itanium processor
  10. Stack architecture
  11. Future architecture
  12. Presentation of research paper
  13. Summary of the topic
 

Assignments

  1. Write an assay on history of computing.  You choose the period that you are interested in.
  2. Write a short report investigating the present day gap between processor speed and memory speed.
  3. Add new instructions by writing new section of microprogram for S1.  Using S1m simulator tools.  Test it with a benchmark program:  add2 r1 r2 r3 ; R[r1] = R[r2]+R[r3],  load2 r1 r2 r3 ; R[r1] = M[R[r2]+R[r3]]  load index.
  4. Midterm project

Handout

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Reading

Tools

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