2110714 Digital Systems

1st semester Aug 2021
classroom online:  Thursday  13:00-16:00
instructor:  Prabhas Chongstitvatana


Today digital technology permeates every corner of our society. There are three big trends that shape our future. The first one is the coming of Artificial Intelligence.  The second one is the rise of Automation.  The last one the revolution of technology to transfer money.  These advancements rely on the power of computing. This class introduces an overview of modern computer system.

The class is divided into three parts. The first one discusses fundamental and performance of the modern processor. The second part discusses multicore processors and Graphic Processing Units. The third part discusses current research in high performance system.


  11 Nov   Final exam (take home) will have 3 questions.  The deadline is 15 Dec 2021.  The questions will be published soon.


40%  assigned work
30%   projects
30%   final take home exam


part 1 Basic

overview of computer architecture
assembly language programming   
          S2 processor instruction and assembly language (pptx)
          S2 processor and instruction set (web)   
interrupt programming   (IoT board simulator)
logic design: basic logic  two-level logic 
         gate, multiplexor, counter
processor:  datapath RISC-V
control unit
processor 4B    its control unit     microprogram control unit (coming soon)
control level simulation
memory design

part 2  Multicore

pipelining   Intro to pipeline    Pipeline implementation RISC-V
super-scalar processors
multicore, synchronization
Programming of Graphics Processing Unit
General Purpose GPU applications
programming with CUDA (by Tongjai Yampaka)

part 3  Current topics

        future of quantum computing



Introduction: Technology    https://youtu.be/_S8QKZsT3wk 
Performance and Power   https://youtu.be/tZJQ9XLl86Y
S2 instruction and use of assembly tools  https://youtu.be/bsqhvtazRBk  
IoT board demo: using the simulator   https://youtu.be/hh3PQTer-KM
basic logic   https://youtu.be/zYQx4JJ8Jyg
simple datapath of RISC-V  https://youtu.be/iGoyB_0qXYE
RISC-V control signals  https://youtu.be/X17kvp8s2P0
RISC-V datapath summary   https://youtu.be/8b3OXS_8Mek
RISC-V control summary    https://youtu.be/zi0XL2zP_xE
Processor 4B design  https://youtu.be/eI3MPIw9iR4
Simulation at control signals level of 4B processor
Pipeline part 1:  pipeline organization and harzard  https://youtu.be/myITS4tAjY8
Pipeline part 2:
   pipeline control a) buffering between stages  https://youtu.be/P87zCotSF1A
   pipeline control b) control signals  https://youtu.be/fUPwkXzkIPA
Memory design part 1: cache memory  https://youtu.be/uKioRhmliVM
Memory design part 2: memory technology, direct-map cache  https://youtu.be/DvJ4CWOYbDk
GPU programming link to video: Introduction to programming CUDA

Next week

9 Sept -- Control unit, start discussion on project prosessor 4B
16 Sept -- simulator of 4B processor
7 Oct -- simulation of control signals of 4B processor 
14 Oct -- pipeline RISC-V
28 Oct -- cache memory
4 Nov -- multi core system


Gate level simulation of  a very simple processor  4B .  You will construct two simulators. One is the instruction level simulator where it can run binary code of the benchmark program.  The second one is the control level simulator where each instruction execution is simulated clock-by-clock.  The second simulator required you to design some functional unit such as ALU in the level of logic gates.  You also need to realise the control events properly.

. . .


Tools for assembly language programming
S2 assembler and simulator    s21-3.zip
S2 assembler and simulator for Mac (written in Python)  s2-for-mac.zip    how to use this tool
Tools for interrupt programming  iot-rz-19.zip (for Windows) xtest.zip   (for Mac, executable only)
Logic design tool:  LogicWork5   tutorial   
Cache design:  cache-simulator (C program), address trace trx.zip
rz36 compiler
s30 package


19 Aug
1.1 )Write simple assembly program S2 to add 5 numbers, all numbers are in registers
1.2) Write simple assembly program S2 to add 2 numbers, they are in memory location 100 and 101 and store the result at location 102.
1.3) Try to assemble and run 1.2, show the snapshot of your screen (with S2 tools)

26 Aug

2.1) Write a program to read port11 (digital input) with interrupt, use this data to plot a graph.  What is the frequency of this wave? Assuming S2 is running at 1MHz and interrupt 0 has period 150 clocks.
2.2) use Logicwork to implement a Full Adder
2.3) try to run demo of 3-bit counter in Logicwork (no submission is required)

2 Sept

3)  Use logicWork to implement a clock.  Input is 50 Hz signal.  The output is 7-segment display. Output has 4 digits, 2 digits for hour, 2 digits for second. One blinking display for 1 sec.  Please realise the counter as synchronous (all flip-flop has the same clock) because it will lessen any timing error. 

9 Sept

4)  Begin to study processor simulator in order to write a simulator for 4B.  An example of such program is the project processor TX1.  Read a bit about it and download its simulator package "tx1-2.zip".  Then, study the source code of its simulator in the directory "simtx1".  Next week we will discuss how the simulator work.

23 Sept

5) Write "instruction level simulator" for 4B.   We will discuss about your simulator in the next class.

7 Oct

6) Write "control level simulation" for 4B

28 Oct

7)    Experiment with cache design

Cache design
     Perform experiment on Cache design with the given trace.  cache-simulator (C program)
      Large trace:   
             This is a trace of a compiler, Som v. 4.1, compiles itself. See this page for the detail about the compiler
              The trace file is trx.zip (5 Mbytes). When unzip it is ~100Mbytes.
              each line contains an address xxx {r,w} r is read w is write
              data is at 0..371192
               instruction is at 400000..410873
               total number of instruction executed is 4520058
               total number of data access is 1044647.

4 Nov

8)  Multi-core  -- using dual core s30, write a program to find maxmimum value of an array of integer. This is similar to sum array example.  Write it in RZ language and compile it with rz36 compiler, then use s30 tools to assemble and run object file in the simulator.

Additional information

Reference textbook: 

Computer Organization and Design: The hardware/software interface (RISC-V edition)
D. Patterson, J. Hennessy, Morgan Kaufman, 2018.  link to Amazon

Kohavi, Switching and finite automata theory, 2009   link to Amazon

Transistor level simulation of an antique CPU.  6502 is used in the iconic Apple II machine.

Project a very simple processor : TX
Latest trend in Processor technology from Intel  (Hot ships 2020)

last update 11 Nov 2021